The invention relates to a method and apparatus for monitoring symmetrical two-wire bus lines and two-wire bus interfaces where the two line wires change polarity in phase opposition.
Serial bus systems are known, for example, in German Patent DE 3,807,418 A1, wherein various aspects of interference immunity are discussed in conjunction with a low cost system design and circuitry. Symmetrical two-wire bus lines and symmetrical interfaces or bus drivers are widely applied in the transmission of digital information in serial fashion. The binary data are transmitted via, for example, intertwisted line wires. The wires can be driven in phase opposition.
Various methods are applied to test the fault-free availability of such lines and of the line drivers driving them, as well as of the line receivers connected thereto. For example, test bits can be inserted into the messages to be transmitted. Devices connected to the bus check the operability of the bus line or the transmitting interface by verifying the correct reception of the test bits. Alternatively, test messages can be sent at a predetermined time interval via the busline. Devices connected to the bus check whether the test messages are received within the system-specific fixed time interval. If the messages are not received, there is a defect in the bus system. Alternatively, an electronic monitoring system can be used to monitor the potential difference between the wires of such a bus line or the potential of the line wires and to test the extent to which corresponding voltage values are situated outside the state change times within defined tolerance windows. The relatively high cost of hardware and software is disadvantageous in these solutions.
U.S. Pat. No. 4,255,809 describes a device in which a rotary movement is detected by two sensors which read a moving mark. The two sensors have a certain offset with respect to one another. The two sensor signals feed two counters whose higher-order outputs are compared with one another. Due to the temporal offset of the sensor signals, the counter readings can be offset with respect to one another. However, in the absence of a mechanical or electrical fault, the higher-order outputs are equal to one another for the preponderant part of the time. This state is evaluated as "fault-free".
It is an object of the invention to provide a method for monitoring symmetrical two-wire bus lines and two-wire bus interfaces, as well as a device for carrying out the method, which manage with a relatively low cost of hardware and software and function independently of voltage potential differences such as, for example, a ground potential offset between individual bus subscribers.
This and other objects are achieved in accordance with the invention wherein the antiphase signals on the two wires of the bus line or on the two bus terminals of the two-wire bus interface are pulse weighted separately with respect to a defined state transition. The pulse chains obtained therefrom are each used for step sequencing an all-step resettable, multistep shift function which is assigned to each of the bus wires and can be serially loaded with a fixed logic level, and the corresponding pulse chains derived analogously from the other bus wire being used for the all-step resetting of the multistep shift function, the procedure being the reverse with respect to a multistep shift function assigned to the other of the bus wires. The logic state of the respectively last-reached step state of a multistep shift function then characterizes the most recent fault state of the other bus wire which can still be detected. According further to the present invention, the pulse weighting can be performed by differentiation, high-pass filtering, or by pulse generation control according to state transition. The edge-triggered generation of corresponding pulses offers the advantage that it is possible to achieve independence from the transmission speed on the bus before and after the occurrence of a fault.
Optimizing or matching the fault tolerance or the possible bit frequency and/or edge steepness can occur if after the detection of a bus fault has been performed, the testing of two-wire buses is rendered possible.
According to the present invention, a device has two high-pass filters, coupled to the bus line or to the two bus terminals of the two-wire bus interface, for differentiating the bus line signals, as well as two shift registers for realizing multistep shift functions. The shift registers each have a serial data input as well a clock input, acting in parallel, and a reset input, acting in parallel, and a serial data output. Depending on the logic type, the data inputs of the two registers can be, for example, permanently connected to the logic level "H". The clock input of each shift register is driven in each case by the output of the high-pass filter assigned to the same bus wire, and the reset input of each shift register is driven in each case by the output of the high-pass filter assigned to the other bus wire. In the event of a fault free bus state, a pulse from a specific state change on one bus wire resets to its complement a logic level clocked in by corresponding state changes on the other bus wire, so that, for example, the logic level "H" can appear at the output of a shift register only in the event of interference and of a consequently absent resetting of the shift register, and that the other bus wire is therefore identified in each case as a fault source. It is advantageous, on the one hand, that the hardware cost of this device is very low, since said filters can be realized as simple RC elements. Furthermore, it is advantageous, on the other hand, that the fault signals are present statically, so that their interrogation and evaluation by means of microprocessors can be performed at any desired points in time and consequently with a conceivably low software cost.
According further to the present invention, it is possible with respect to the shift registers provided according to the invention to have recourse to single-piece, integrated logic circuits, so that as a whole the monitoring device can be realized in a very space-saving and cost-effective fashion. The topographies of a plurality of shift registers consideration are available as silicon compilable standard cells, and corresponding RC filters manage with very low capacitances or can be replaced by likewise silicon-compilable, edge-triggered monostable multivibrators or timing structures, the device according to the invention can also be co-integrated using highly reliable technology on-chip with monolithic bus circuits, in conjunction with a very low cost outlay.
Because of a bus fault tolerance and/or cutoff frequency that can be influenced or selected, a device developed according to the invention is suitable as a universal, silicon-compilable standard cell for monitoring symmetrical two-wire bus lines and two wire bus interfaces. Due to the possibility of defined variation in the duration of individual pulses generated in the course of the pulse weighting as control pulses for the shift registers and/or of defined variation in the bit length of the fault tolerance, an appropriately developed device also permits testing of a two-wire bus which is suspected of having interference, specifically with or without the use of a special bus test signal.